Generally, a programmable logic device (PLD) may include programmable logic regions that are disposed on the device in a two-dimensional array of intersecting rows and columns. Each logic region is programmed or customized to perform a variety of functions to produce output signals. Input and output signals of each logic region are routed over interconnects (e.g., conductive lines) between logic regions to route selected signals throughout the PLD.
In order to convey signals between two logic regions, a tri-stated bidirectional driver circuit can be implemented in each logic region. The tri-stated bidirectional driver circuit in each logic region passes signals via a conductive line that is shared by the two logic regions.
During power-up, the two bidirectional driver circuits are activated simultaneously and each of the bidirectional driver circuits simultaneously outputs a drive signal onto the conductive line between the logic regions. Current contention can often occur when the two bidirectional driver circuits attempt to drive the conductive line at the same time. This causes current leakage and damage to the integrated circuit. In scenarios where there is an unused logic row (e.g., a resource row of the PLD having unused logic regions), that whole row is often skipped (e.g., not programmed) during configuration of the PLD. In this case, additional configuration is required to skip the unused logic row at the configuration stage of the PLD, which can result in an undesirable increase in design cost for the PLD.